Dual Dopant Source/Drain Regions and Methods of Forming Same

ABSTRACT

A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

PRIORITY CLAIM AND CROSS-REFERENCE

This patent is a divisional of U.S. application Ser. No 16/887,154,filed on May 29, 2020, which application is hereby incorporated byreference herein as if reproduced in its entirety.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as, for example, personal computers, cell phones, digital cameras,and other electronic equipment. Semiconductor devices are typicallyfabricated by sequentially depositing insulating or dielectric layers,conductive layers, and semiconductor layers of material over asemiconductor substrate, and patterning the various material layersusing lithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallow more components to be integrated into a given area.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates an example of a FinFET in a three-dimensional view,in accordance with some embodiments.

FIGS. 2, 3, 4, 5, 6, 7, 8A, 8B, 9A, 9B, 10, 11, 12A, 12B, 12C, 13A, 13B,14A, 14B, 15A, 15B, 15C, 16, 17, 18A, 18B, 19A, 19B, 20A, 20B, 21A, 21B,21C, 22A, 22B, 23A, and 23B are cross-sectional and top-down views ofintermediate stages in the manufacturing of FinFETs, in accordance withsome embodiments.

FIG. 15D illustrates impurity concentrations in a device in accordancewith some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Various embodiments include implanting two different types of dopantsinto a source/drain region for improved junction abruptness (e.g.,reduced leakage current) and reduced source/drain contact resistance. Inan embodiment method, first dopants are implanted into a source/drainregion followed by an implantation of second dopants. The first dopantsare a different element than the second dopants, and the first dopantsmay have a lower formation enthalpy than the second dopants. Forexample, the first dopants may comprise arsenic, carbon, antimony, orthe like, and the second dopants may comprise phosphorus, or the like.In particular embodiments, the arsenic is implanted into thesource/drain regions followed by a phosphorus dimer (P2) implantation.As a result of its lower formation enthalpy, the first dopants are moreattracted to and form more stable bonds with vacancies in thesource/drain region. For example, the first dopants may be used toreduce diffusion of the second dopants and reduce the binding of thesecond dopants with the vacancies. By reducing diffusion of the seconddopant, a higher concentration of the second dopant may be achieved in acontact area of the source/drain region, thereby reducing source/draincontact resistance. Further, the use of two different elements asdopants allows for a junction with improved abruptness and lessdiffusion, thereby providing improved short channel control (e.g., tocounter the effects of drain-induced barrier lowering (DIBL) in advancedprocess nodes). Various embodiments may provide one or more of thefollowing non-limiting advantages: improved junction abruptness, reduceddiffusion of the second dopants, and reduced source/drain contactresistance.

FIG. 1 illustrates an example of a FinFET in a three-dimensional view,in accordance with some embodiments. The FinFET comprises a fin 52 on asubstrate 50 (e.g., a semiconductor substrate). Isolation regions 56 aredisposed in the substrate 50, and the fin 52 protrudes above and frombetween neighboring isolation regions 56. Although the isolation regions56 are described/illustrated as being separate from the substrate 50, asused herein the term “substrate” may be used to refer to just thesemiconductor substrate or a semiconductor substrate inclusive ofisolation regions. Additionally, although the fin 52 is illustrated as asingle, continuous material as the substrate 50, the fin 52 and/or thesubstrate 50 may comprise a single material or a plurality of materials.In this context, the fin 52 refers to the portion extending between theneighboring isolation regions 56.

A gate dielectric layer 92 is along sidewalls and over a top surface ofthe fin 52, and a gate electrode 94 is over the gate dielectric layer92. Source/drain regions 82 are disposed in opposite sides of the fin 52with respect to the gate dielectric layer 92 and gate electrode 94. FIG.1 further illustrates reference cross-sections that are used in laterfigures. Cross-section A-A is along a longitudinal axis of the gateelectrode 94 and in a direction, for example, perpendicular to thedirection of current flow between the source/drain regions 82 of theFinFET. Cross-section B-B is perpendicular to cross- section A-A and isalong a longitudinal axis of the fin 52 and in a direction of, forexample, a current flow between the source/drain regions 82 of theFinFET. Cross-section C-C is parallel to cross-section A-A and extendsthrough a source/drain region of the FinFET. Subsequent figures refer tothese reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context ofFinFETs formed using a gate-last process. In other embodiments, agate-first process may be used. Also, some embodiments contemplateaspects used in planar devices, such as planar FETs, nanostructure(e.g., nanosheet, nanowire, gate-all-around, or the like) field effecttransistors (NSFETs), or the like.

FIGS. 2 through 23B are cross-sectional views of intermediate stages inthe manufacturing of FinFETs, in accordance with some embodiments. FIGS.2 through 7 illustrate reference cross-section A-A illustrated in FIG.1, except for multiple fins/FinFETs. FIGS. 8A, 9A, 18A, 19A, 20A, 21A,22A, and 23A are illustrated along reference cross-section A-Aillustrated in FIG. 1, and FIGS. 8B, 9B, 10, 12A, 13A, 14A, 15A, 16, 17,18B, 19B, 20B, 21B, 22B, and 23B are illustrated along a similarcross-section B-B illustrated in FIG. 1, except for multiplefins/FinFETs. FIGS. 12B, 12C, 15B, and 15C are illustrated alongreference cross-section C-C illustrated in FIG. 1, except for multiplefins/FinFETs.

In FIG. 2, a substrate 50 is provided. The substrate 50 may be asemiconductor substrate, such as a bulk semiconductor, asemiconductor-on-insulator (SOI) substrate, or the like, which may bedoped (e.g., with a p-type or an n-type dopant) or undoped. Thesubstrate 50 may be a wafer, such as a silicon wafer. Generally, an SOIsubstrate is a layer of a semiconductor material formed on an insulatorlayer. The insulator layer may be, for example, a buried oxide (BOX)layer, a silicon oxide layer, or the like. The insulator layer isprovided on a substrate, typically a silicon or glass substrate. Othersubstrates, such as a multi-layered or gradient substrate may also beused. In some embodiments, the semiconductor material of the substrate50 may include silicon; germanium; a compound semiconductor includingsilicon carbide, gallium arsenide, gallium phosphide, indium phosphide,indium arsenide, and/or indium antimonide; an alloy semiconductorincluding silicon-germanium, gallium arsenide phosphide, aluminum indiumarsenide, aluminum gallium arsenide, gallium indium arsenide, galliumindium phosphide, and/or gallium indium arsenide phosphide; orcombinations thereof.

The substrate 50 has an n-type region 50N and a p-type region 50P. Then-type region 50N can be for forming n-type devices, such as NMOStransistors, e.g., n-type FinFETs. The p-type region 50P can be forforming p-type devices, such as PMOS transistors, e.g., p-type FinFETs.The n-type region 50N may be physically separated from the p-type region50P (as illustrated by divider 51), and any number of device features(e.g., other active devices, doped regions, isolation structures, etc.)may be disposed between the n-type region 50N and the p-type region 50P.

In FIG. 3, fins 52 are formed in the substrate 50. The fins 52 aresemiconductor strips. In some embodiments, the fins 52 may be formed inthe substrate 50 by etching trenches in the substrate 50. The etchingmay be any acceptable etch process, such as a reactive ion etch (RIE),neutral beam etch (NBE), the like, or a combination thereof. The etchmay be anisotropic.

The fins may be patterned by any suitable method. For example, the fins52 may be patterned using one or more photolithography processes,including double-patterning or multi-patterning processes. Generally,double-patterning or multi-patterning processes combine photolithographyand self-aligned processes, allowing patterns to be created that have,for example, pitches smaller than what is otherwise obtainable using asingle, direct photolithography process. For example, in one embodiment,a sacrificial layer is formed over a substrate and patterned using aphotolithography process. Spacers are formed alongside the patternedsacrificial layer using a self-aligned process. The sacrificial layer isthen removed, and the remaining spacers may then be used to pattern thefins. In some embodiments, the mask (or other layer) may remain on thefins 52.

In FIG. 4, an insulation material 54 is formed over the substrate 50 andbetween neighboring fins 52. The insulation material 54 may be an oxide,such as silicon oxide, a nitride, the like, or a combination thereof,and may be formed by a high density plasma chemical vapor deposition(HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material depositionin a remote plasma system and post curing to make it convert to anothermaterial, such as an oxide), the like, or a combination thereof. Otherinsulation materials formed by any acceptable process may be used. Inthe illustrated embodiment, the insulation material 54 is silicon oxideformed by a FCVD process. An anneal process may be performed once theinsulation material is formed. In an embodiment, the insulation material54 is formed such that excess insulation material 54 covers the fins 52.Although the insulation material 54 is illustrated as a single layer,some embodiments may utilize multiple layers. For example, in someembodiments a liner (not shown) may first be formed along a surface ofthe substrate 50 and the fins 52. Thereafter, a fill material, such asthose discussed above may be formed over the liner.

In FIG. 5, a removal process is applied to the insulation material 54 toremove excess insulation material 54 over the fins 52. In someembodiments, a planarization process such as a chemical mechanicalpolish (CMP), an etch-back process, combinations thereof, or the likemay be utilized. The planarization process exposes the fins 52 such thattop surfaces of the fins 52 and the insulation material 54 are levelafter the planarization process is complete. In embodiments in which amask remains on the fins 52, the planarization process may expose themask or remove the mask such that top surfaces of the mask or the fins52, respectively, and the insulation material 54 are level after theplanarization process is complete.

In FIG. 6, the insulation material 54 is recessed to form Shallow TrenchIsolation (STI) regions 56. The insulation material 54 is recessed suchthat upper portions of fins 52 in the n-type region 50N and in thep-type region 50P protrude from between neighboring STI regions 56.Further, the top surfaces of the STI regions 56 may have a flat surfaceas illustrated, a convex surface, a concave surface (such as dishing),or a combination thereof. The top surfaces of the STI regions 56 may beformed flat, convex, and/or concave by an appropriate etch. The STIregions 56 may be recessed using an acceptable etching process, such asone that is selective to the material of the insulation material 54(e.g., etches the material of the insulation material 54 at a fasterrate than the material of the fins 52). For example, an oxide removalusing, for example, dilute hydrofluoric (dHF) acid may be used.

The process described with respect to FIGS. 2 through 6 is just oneexample of how the fins 52 may be formed. In some embodiments, the finsmay be formed by an epitaxial growth process. For example, a dielectriclayer can be formed over a top surface of the substrate 50, and trenchescan be etched through the dielectric layer to expose the underlyingsubstrate 50. Homoepitaxial structures can be epitaxially grown in thetrenches, and the dielectric layer can be recessed such that thehomoepitaxial structures protrude from the dielectric layer to formfins. Additionally, in some embodiments, heteroepitaxial structures canbe used for the fins 52. For example, the fins 52 in FIG. 5 can berecessed, and a material different from the fins 52 may be epitaxiallygrown over the recessed fins 52. In such embodiments, the fins 52comprise the recessed material as well as the epitaxially grown materialdisposed over the recessed material. In an even further embodiment, adielectric layer can be formed over a top surface of the substrate 50,and trenches can be etched through the dielectric layer. Heteroepitaxialstructures can then be epitaxially grown in the trenches using amaterial different from the substrate 50, and the dielectric layer canbe recessed such that the heteroepitaxial structures protrude from thedielectric layer to form the fins 52. In some embodiments wherehomoepitaxial or heteroepitaxial structures are epitaxially grown, theepitaxially grown materials may be in situ doped during growth, whichmay obviate prior and subsequent implantations although in situ andimplantation doping may be used together.

Still further, it may be advantageous to epitaxially grow a material inn-type region 50N (e.g., an NMOS region) different from the material inp-type region 50P (e.g., a PMOS region). In various embodiments, upperportions of the fins 52 may be formed from silicon-germanium(Si_(x)Ge_(1-x), where x can be in the range of 0 to 1), siliconcarbide, pure or substantially pure germanium, a III-V compoundsemiconductor, a II-VI compound semiconductor, or the like. For example,the available materials for forming III-V compound semiconductorinclude, but are not limited to, indium arsenide, aluminum arsenide,gallium arsenide, indium phosphide, gallium nitride, indium galliumarsenide, indium aluminum arsenide, gallium antimonide, aluminumantimonide, aluminum phosphide, gallium phosphide, and the like.

Further in FIG. 6, appropriate wells (not shown) may be formed in thefins 52 and/or the substrate 50. In some embodiments, a P well may beformed in the n-type region 50N, and an N well may be formed in thep-type region 50P. In some embodiments, a P well or an N well are formedin both the n-type region 50N and the p-type region 50P.

In the embodiments with different well types, the different implantsteps for the n-type region 50N and the p-type region 50P may beachieved using a photoresist and/or other masks (not shown). Forexample, a photoresist may be formed over the fins 52 and the STIregions 56 in the n-type region 50N. The photoresist is patterned toexpose the p-type region 50P of the substrate 50. The photoresist can beformed by using a spin-on technique and can be patterned usingacceptable photolithography techniques. Once the photoresist ispatterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially preventn-type impurities from being implanted into the n-type region 50N. Then-type impurities may be phosphorus, arsenic, antimony, or the like, andimplanted in the region to a concentration of equal to or less than 10¹⁸cm⁻³, such as between about 10¹⁶ cm⁻³ and about 10¹⁸ cm⁻³. After theimplant, the photoresist is removed, such as by an acceptable ashingprocess.

Following the implanting of the p-type region 50P, a photoresist isformed over the fins 52 and the STI regions 56 in the p-type region 50P.The photoresist is patterned to expose the n-type region 50N of thesubstrate 50. The photoresist can be formed by using a spin-on techniqueand can be patterned using acceptable photolithography techniques. Oncethe photoresist is patterned, a p-type impurity implant may be performedin the n-type region 50N, and the photoresist may act as a mask tosubstantially prevent p-type impurities from being implanted into thep-type region 50P. The p-type impurities may be boron, boron fluoride,indium, or the like implanted in the region to a concentration of equalto or less than 10¹⁸ cm⁻³, such as between about 10¹⁶ cm⁻³ and about10¹⁸ cm⁻³. After the implant, the photoresist may be removed, such as byan acceptable ashing process.

After the implants of the n-type region 50N and the p-type region 50P,an anneal may be performed to repair implant damage and to activate thep-type and/or n-type impurities that were implanted. In someembodiments, the grown materials of epitaxial fins may be in situ dopedduring growth, which may obviate the implantations, although in situ andimplantation doping may be used together.

In FIG. 7, a dummy dielectric layer 60 is formed on the fins 52. Thedummy dielectric layer 60 may be, for example, silicon oxide, siliconnitride, a combination thereof, or the like, and may be deposited orthermally grown according to acceptable techniques. A dummy gate layer62 is formed over the dummy dielectric layer 60, and a mask layer 64 isformed over the dummy gate layer 62. The dummy gate layer 62 may bedeposited over the dummy dielectric layer 60 and then planarized, suchas by a CMP. The mask layer 64 may be deposited over the dummy gatelayer 62. The dummy gate layer 62 may be a conductive or non-conductivematerial and may be selected from a group including amorphous silicon,polycrystalline-silicon (polysilicon), poly-crystallinesilicon-germanium (poly-SiGe), metallic nitrides, metallic silicides,metallic oxides, and metals. The dummy gate layer 62 may be deposited byphysical vapor deposition (PVD), CVD, sputter deposition, or othertechniques for depositing the selected material. The dummy gate layer 62may be made of other materials that have a high etching selectivity fromthe etching of isolation regions, e.g., the STI regions 56 and/or thedummy dielectric layer 60. The mask layer 64 may include one or morelayers of, for example, silicon nitride, silicon oxynitride, or thelike. In this example, a single dummy gate layer 62 and a single masklayer 64 are formed across the n-type region 50N and the p-type region50P. It is noted that the dummy dielectric layer 60 is shown coveringonly the fins 52 for illustrative purposes only. In some embodiments,the dummy dielectric layer 60 may be deposited such that the dummydielectric layer 60 covers the STI regions 56, extending over the STIregions and between the dummy gate layer 62 and the STI regions 56.

FIGS. 8A through 16B illustrate various additional steps in themanufacturing of embodiment devices. FIGS. 8A through 16B illustratefeatures in either of the n-type region 50N and the p-type region 50P.For example, the structures illustrated in FIGS. 8A through 16B may beapplicable to both the n-type region 50N and the p-type region 50P.Differences (if any) in the structures of the n-type region 50N and thep-type region 50P are described in the text accompanying each figure.

In FIGS. 8A and 8B, the mask layer 64 (see FIG. 7) may be patternedusing acceptable photolithography and etching techniques to form masks74. The pattern of the masks 74 then may be transferred to the dummygate layer 62. In some embodiments (not illustrated), the pattern of themasks 74 may also be transferred to the dummy dielectric layer 60 by anacceptable etching technique to form dummy gates 72. The dummy gates 72cover respective channel regions 58 of the fins 52. The pattern of themasks 74 may be used to physically separate each of the dummy gates 72from adjacent dummy gates. The dummy gates 72 may also have a lengthwisedirection substantially perpendicular to the lengthwise direction ofrespective epitaxial fins 52.

Further in FIGS. 8A and 8B, gate seal spacers 80 can be formed onexposed surfaces of the dummy gates 72, the masks 74, and/or the fins52. A thermal oxidation or a deposition followed by an anisotropic etchmay form the gate seal spacers 80. The gate seal spacers 80 may beformed of silicon oxide, silicon nitride, silicon oxynitride, or thelike.

After the formation of the gate seal spacers 80, implants for lightlydoped source/drain (LDD) regions (not explicitly illustrated) may beperformed. In the embodiments with different device types, similar tothe implants discussed above in FIG. 6, a mask, such as a photoresist,may be formed over the n-type region 50N, while exposing the p-typeregion 50P, and appropriate type (e.g., p-type) impurities may beimplanted into the exposed fins 52 in the p-type region 50P. The maskmay then be removed. Subsequently, a mask, such as a photoresist, may beformed over the p-type region 50P while exposing the n-type region 50N,and appropriate type impurities (e.g., n-type) may be implanted into theexposed fins 52 in the n-type region 50N. The mask may then be removed.The n-type impurities may be the any of the n-type impurities previouslydiscussed, and the p-type impurities may be the any of the p-typeimpurities previously discussed. The lightly doped source/drain regionsmay have a concentration of impurities of from about 10¹⁵ cm⁻³ to about10¹⁹ cm⁻³. An anneal may be used to repair implant damage and toactivate the implanted impurities.

In FIGS. 9A and 9B, gate spacers 86 are formed on the gate seal spacers80 along sidewalls of the dummy gates 72 and the masks 74. The gatespacers 86 may be formed by conformally depositing an insulatingmaterial and subsequently anisotropically etching the insulatingmaterial. The insulating material of the gate spacers 86 may be siliconoxide, silicon nitride, silicon oxynitride, silicon carbonitride, acombination thereof, or the like.

It is noted that the above disclosure generally describes a process offorming spacers and LDD regions. Other processes and sequences may beused. For example, fewer or additional spacers may be utilized,different sequence of steps may be utilized (e.g., the gate seal spacers80 may not be etched prior to forming the gate spacers 86, yielding“L-shaped” gate seal spacers, spacers may be formed and removed, and/orthe like. Furthermore, the n-type and p-type devices may be formed usinga different structures and steps. For example, LDD regions for n-typedevices may be formed prior to forming the gate seal spacers 80 whilethe LDD regions for p-type devices may be formed after forming the gateseal spacers 80.

In FIGS. 10 through 15, epitaxial source/drain regions 82 are formed inthe fins 52. The epitaxial source/drain regions 82 are formed in thefins 52 such that each dummy gate 72 is disposed between respectiveneighboring pairs of the epitaxial source/drain regions 82. In someembodiments the epitaxial source/drain regions 82 may extend into, andmay also penetrate through, the fins 52. In some embodiments, the gatespacers 86 are used to separate the epitaxial source/drain regions 82from the dummy gates 72 by an appropriate lateral distance so that theepitaxial source/drain regions 82 do not short out subsequently formedgates of the resulting FinFETs. A material of the epitaxial source/drainregions 82 may be selected to exert stress in the respective channelregions 58, thereby improving performance.

The epitaxial source/drain regions 82 in the n-type region 50N may bedifferent and formed separately from the epitaxial source/drain regions82 in the p-type region 50P. For example, FIGS. 10 11, 12A, 13A, 14A,and 15A illustrate cross-sectional views along line B-B of FIG. 1 offorming the epitaxial source/drain regions 82 in the n-type region 50N.The steps described in FIGS. 10 through 15A may be performed while thep-type region 50P (not explicitly illustrated) is masked. In FIG. 10,source/drain regions of the fins 52 in the n-type region 50N arepatterned to form recesses 20 in the fins 52. For example, recesses 20may be formed on in the fins 52 on opposing sides of the dummy gategates 72 (e.g., see FIG. 19B), such as between adjacent dummy gates 72.Patterning the recesses 20 may be achieved by, for example, acombination of photolithography and etching. In some embodiments, thefins 52 may be over etched such that the recesses 20 extend directlyunder the gate spacers 86.

In FIG. 11, optional epitaxial regions 22 are grown in the recesses 20.The epitaxial regions 22 may only partially fill the recesses 20. Forexample, the epitaxial regions 22 may be grown to cover sides andbottoms of the recesses 20. The epitaxial regions 22 may be grown by anyacceptable process and may include any acceptable material, such asappropriate for n-type FinFETs. For example, if the fin 52 is silicon,the epitaxial regions 22 may include silicon, silicon carbide, siliconphosphide, or the like. In some embodiments, a material of the epitaxialregions 22 in the n-type region 50N may be chosen to exert a tensilestrain on the channel regions 58. In some embodiments, the epitaxialregions 22 have a thickness T1 in a range of about 3 nm to about 7 nm.

The epitaxial regions 22 and/or the fins 52 may be implanted withdopants during the epitaxy using an in-situ doping process. For example,first n-type impurities may be flowed into the deposition chamber whilethe epitaxial regions 22 are grown. The first n-type impuritiesimplanted in the epitaxial regions 22 may be phosphorus, arsenic,carbon, antimony, or the like. The epitaxial regions 22 may have animpurity concentration in a range of about 5×10¹⁹ cm⁻³ to about 2×10²⁰cm⁻³, for example. In other embodiments, the epitaxial regions 22 mayhave a different impurity concentration. The impurity concentration inthe epitaxial regions 22 may be constant throughout the epitaxialregions 22 or it may be varied. For example, the epitaxial regions 22may have a gradient impurity concentration that increases in a directionaway from sidewalls of the fins 52 on which the epitaxial regions 22 isgrown.

In FIG. 12A, the epitaxial growth process may continue to fill remainingportions of the recesses 20 with epitaxial regions 24 a and 24 b.Growing the epitaxial regions 24 a and 24 b may be performed in-situ(e.g., in a same chamber) as the epitaxial regions 22 and using a sameprocess as the epitaxial regions 22. Further, the epitaxial regions 24 aand 24 b may comprise a same material as the epitaxial regions 22, suchas, silicon, silicon carbide, silicon phosphide, or the like. In someembodiments, a material of the epitaxial regions 24 a and 24 b in then-type region 50N may be chosen to exert a same type of stress (e.g.,tensile) on the channel regions 58 as the epitaxial regions 22. In someembodiments, the epitaxial regions 24 a and 24 b have a combinedthickness T2 in a range of about 50 nm to about 70 nm. The thickness T2may be measured from a topmost surface of the epitaxial regions 24 b toa bottommost point of the epitaxial regions 24 a.

The epitaxial regions 24 a, the epitaxial regions 24 b, and/or the fins52 may be implanted with dopants during the epitaxy using an in-situdoping process. For example, second n-type impurities may be flowed intothe deposition chamber while the epitaxial regions 22 are grown. Thesecond n-type impurities implanted in the epitaxial regions 24 a and 24b may be phosphorus, arsenic, carbon, antimony, or the like. In someembodiments, the second n-type may be a different element than the firstn-type impurities implanted in the epitaxial regions 22. For example, ina specific embodiment, the epitaxial regions 22 may be implanted witharsenic, and the epitaxial regions 24 a and 24 b may be implanted withphosphorus. Other combinations of n-type impurities may be used in otherembodiments.

Further, a dopant concentration of the second n-type impurities may bedifferent in the epitaxial regions 24 a and 24 b. For example, aconcentration of the second n-type impurities in the epitaxial regions24 b may be greater than the second n-type impurities in the epitaxialregions 24 a. This may be achieved, for example, by varying a flow rateand/or concentration of a dopant gas flowed into the process chamberduring the epitaxy. In some embodiments, the epitaxial regions 24 a havean impurity concentration in a range of about 5×10²⁰ cm⁻³ to about 10²¹cm⁻³, and the epitaxial regions 24 b have an impurity concentration inin a range of about 10²¹ cm⁻³ to about 3×10²¹ cm⁻³. In otherembodiments, the epitaxial regions 24 a and/or 24 b may have differentimpurity concentrations. The impurity concentration in the epitaxialregions 24 a and/or 24 b may be constant throughout respective epitaxialregions 24 a/24 b, or it may be varied. For example, the epitaxialregions 24 a/24 b may each have a gradient, impurity concentration thatincreases in a direction towards a top surface of the fins 52.

Thus, epitaxial source/drain regions 82 are formed. The epitaxialsource/drain regions 82 includes the epitaxial regions 22, 24 a, and 24b. The epitaxial regions 22 include first impurities (e.g., arsenic, orthe like), and the epitaxial regions 24 a and 24 b include secondimpurities (e.g., phosphorus, or the like). The epitaxial regions 22 mayline sides and bottoms of the epitaxial regions 24 a/24 b.Alternatively, one or more of the epitaxial regions 22, 24 a, or 24 bmay be omitted from the epitaxial source/drain regions 82.

The epitaxial source/drain regions 82 may have surfaces raised fromrespective surfaces of the fins 52 and may have facets. As a result ofthe epitaxy processes used to form the epitaxial source/drain regions82, upper surfaces of the epitaxial source/drain regions have facetswhich expand laterally outward beyond sidewalls of the fins 52. In someembodiments, these facets cause adjacent source/drain regions 82 of asame FinFET to merge as illustrated by FIG. 12B. In other embodiments,adjacent source/drain regions 82 remain separated after the epitaxyprocess is completed as illustrated by FIG. 12C. In the embodimentsillustrated in FIGS. 12B and 12C, gate spacers 86 are formed covering aportion of the sidewalls of the fins 52 that extend above the STIregions 56 thereby blocking the epitaxial growth. In some otherembodiments, the spacer etch used to form the gate spacers 86 may beadjusted to remove the spacer material to allow the epitaxially grownregion to extend to the surface of the STI region 56.

FIGS. 13A through 14B illustrate additional implantation steps, whichare formed on the epitaxial source/drain regions 82 after the epitaxialsource/drain regions 82 are fully grown in some embodiments. In FIGS.13A and 13B, a first implantation 26 is performed on the epitaxialsource/drain regions 82. The first implantation 26 may be performedin-situ with forming the epitaxial source/drain regions 82 or it may beperformed ex-situ of forming the epitaxial source/drain regions 82.

In some embodiments, the first implantation 26 implants third n-typeimpurities into the epitaxial source/drain regions 82. The thirdimpurities may be selected to have a relatively low formation enthalpy,and may be, arsenic, antimony, carbon, or the like. As will be explainedin greater detail below, due to its relatively low formation enthalpy,the third impurities are more attracted to vacancies (V) in theepitaxial source/drain regions 82, and the third impurities may forminactive clusters with the vacancies. For example, in embodiments wherethe third impurities are arsenic, As₄V may form as a relatively stablecomplex (e.g., be deactivated to from an inactive cluster). Accordingly,the third impurities help reduce diffusion of fourth impurities that aresubsequently implanted into the epitaxial source/drain regions 82. Forexample, vacancies in the silicon lattice has a stronger attraction tothe third impurities (e.g., arsenic) than the fourth impurities (e.g.,phosphorus). Accordingly, diffusion of the fourth impurity may be slowedif the vacancies are consumed by forming stable complexes with the thirdimpurity. As a result, source/drain contact resistance can be lowered.Further, implanting the third impurities may provide improved junctionabruptness and reduced diffusion compared to a junction formed byimplanting only the fourth impurities described below. The thirdimpurities implanted in the first implantation 26 may be the same ordifferent as the first impurities in the epitaxial regions 22.

The first implantation 26 may use arsenic, antimony, carbon, or the likeas a dopant gas. Other carrier gases (e.g., nitrogen, argon, helium, orthe like) may also be present. The first implantation 26 may beperformed at an implantation energy in a range of about 2 keV to about20 keV, such as about 4 keV. An implantation dosage of the firstimplantation 26 may be in a range of about 5×10¹⁴ cm⁻³ to about 10²²cm⁻³. An implantation angle of the first implantation 26 may be in arange of about 3° to about 15°, and a rotation angle of the firstimplantation 26 may in a range of 0° to 360°. For example, theimplantation angle may refer to an angle at which the third impuritiesare implanted from above into the epitaxial source/drain regions 82relative a major surface of the substrate. Further, a rotation angle mayrefer to the rotation of the wafer 10 around the process chamber duringthe first implantation 26. For example, referring to FIG. 13B, a topdown view of a process chamber 200 is illustrated. The firstimplantation 26 may be performed in the process chamber 200. The processchamber 200 includes a platen 202, which supports the wafer 10 duringthe first implantation 26. The platen may further be connected to amotor, which rotates the wafer 10 according to a rotation angle of thefirst implantation 26 as indicated by arrow 28. The wafer 10 may berotated any number times. For example, in some embodiments, the wafer 10is not rotated throughout an entire duration of the first implantation26. In other embodiments, the wafer 10 is rotated 90° twice. In yetother embodiments, the wafer 10 is rotated 45° four times. The rotationangle and number of times the wafer is rotated may affect a post-annealimplantation profile of the completed structure (e.g., see FIGS. 15Athrough 17). Accordingly, by adjusting the rotation angle and rotationtimes during the first implantation 26, different implantation profilescan be achieved. Although FIG. 13B illustrates a process chamber 200with a specific configuration processing a single wafer 10, otherconfigurations are also possible, and a different number of wafers maybe processed concurrently in the process chamber 200.

Next, in FIGS. 14A and 14B, a second implantation 30 is performed on theepitaxial source/drain regions 82. The second implantation 30 may beperformed in-situ or ex-situ of the first implantation 26. In someembodiments, no annealing processes are performed between the firstimplantation 26 and the second implantation 30.

In some embodiments, the second implantation 30 implants fourthimpurities into the epitaxial source/drain regions 82. The fourthimpurities may be selected to have a relatively high formation enthalpycompared to the third impurities implanted in the first implantation 26.For example, the fourth impurities may comprise phosphorus (e.g.,phosphorus dimer (P2)), or the like. In some particular embodiments, thefirst implantation 26 implants arsenic, and the second implantation 30implants phosphorus dimer. Due to the relatively high formation enthalpyof the fourth impurities compared to the third impurities, the fourthimpurities are less attracted to vacancies (V) in the epitaxialsource/drain regions 82. For example, the third impurities may formstable complexes with the vacancies, thereby reducing deactivation(e.g., through the formation of complexes of the fourth impurities andthe vacancies) and diffusion of the fourth impurities. As a result,contact resistance can be lowered due to a higher concentration of thefourth impurities in a contact area of the epitaxial source/drainregions 82 (e.g., top portions of the epitaxial source/drain regions82). Further, including third impurities may provide improved junctionabruptness and reduced diffusion than a junction formed by implantingonly the fourth impurities.

The second implantation 30 may use phosphorus (e.g., phosphorus dimer(P2)), or the like as a dopant gas. Other carrier gases (e.g., nitrogen,argon, helium, or the like) may also be present. The second implantation30 may be performed at an implantation energy in a range of about 2 keVto about 20 keV. An implantation dosage of the second implantation 30may be at least about 4×10¹⁵ cm⁻³, such as in a range of about 10¹⁸ cm⁻³to about 10²² cm⁻³. It has been observed that by implanting the fourthimpurities at a high dose (e.g., in the above range), source/draincontact resistance can be reduced by providing increased dopants in acontact area of the epitaxial source/drain regions 82. An implantationangle of the second implantation 30 may be in a range of about 3° toabout 15°, and a rotation angle of the second implantation 30 may be ina range of 0° to 360°. For example, the implantation angle may refer toan angle at which the fourth impurities are implanted from above intothe epitaxial source/drain regions 82 relative a major surface of thesubstrate. Further, a rotation angle may refer to the rotation of thewafer 10 around the process chamber during the second implantation 30.For example, referring to FIG. 14B, a top down view of the processchamber 200 is illustrated. The second implantation 30 may be performedin the same process chamber 200 as the first implantation 26.Alternatively, the second implantation 30 may be performed in adifferent process chamber 200. The wafer 10 is rotated on the platen 202according to a rotation angle of the second implantation 30 as indicatedby arrow 32. The wafer 10 may be rotated any number times. For example,in some embodiments, the wafer 10 is not rotated throughout an entireduration of the second implantation 30. In other embodiments, the wafer10 is rotated 90° twice during the second implantation 30. In yet otherembodiments, the wafer 10 is rotated 45° four times during the secondimplantation 30. The rotation angle and number of times the wafer isrotated may affect a post-anneal implantation profile of the completedstructure (e.g., see FIGS. 15A through 17). Accordingly, by adjustingthe rotation angle and rotation times during the first implantation 26and/or the second implantation 30, different implantation profiles canbe achieved. Although FIG. 14B illustrates a process chamber 200 with aspecific configuration processing a single wafer 10, otherconfigurations are also possible, and a different number of wafers maybe processed concurrently in the process chamber 200.

Subsequently, an annealing process may be performed to activate thethird dopants and the fourth dopants. For example, in some embodiments,the annealing process may include a microsecond anneal (μSSA) followedby a laser spike anneal (LSA). In some embodiments, the junction profileof fourth dopants (e.g., phosphorus) may be the same after the annealingprocess (e.g., after the μSSA/LSA) as before the annealing process.Accordingly, the implantation of a lower formation enthalpy element mayhelp reduce diffusion during the annealing process. The μSSA may beperformed at a temperature in a range of about 1050° C. to about 1150°C., and the LSA may be performed at a temperature in a range of about1100° C. to about 1250° C. Other anneal process(es) may be used in otherembodiments.

FIGS. 15A, 15B, and 15C illustrate the resulting structure after theannealing process according to some embodiments. FIG. 15A illustratesthe structure along the line B-B of FIG. 1; FIG. 15B illustrates thestructure along the line C-C of FIG. 1 for a merged epitaxialsource/drain regions 82; and FIG. 15C illustrates the structure alongthe line C-C of FIG. 1 for unmerged epitaxial source/drain regions 82.As illustrated, doped regions 34 and 36 are formed at a top of theepitaxial source/drain regions 82 and the fins 52. The doped regions 34comprise the third impurities having the relatively low formationenthalpy, and the doped regions 36 comprise the fourth impurities havingthe relatively high formation enthalpy. In the embodiments of FIGS. 15A,15B, and 15C, the sides and bottoms of the doped regions 36 may becovered by the doped regions 34. For example, the doped regions 34 mayseparate the doped regions 36 from the fins 52 and lower portions of theepitaxial source/drain regions 82. Further, doped regions 34 and 36 mayfurther include additional impurities, such as, the first and/or secondimpurities implanted in the epitaxial source/drain regions 82 (e.g.,implanted in-situ of respective epitaxial regions 22, 24A, and 24B). Theoriginal boundaries for the epitaxial regions 22, 24A, and 24B areillustrated in ghost for reference.

The doped regions 34 provides a steeper junction for improved shortchannel control (e.g., improved DIBL with channel length less than,e.g., 10 nm and reduced leakage current). For example, in experimentaldata, off current was reduced by at least 20% in embodiment transistorswhere both the third and fourth impurities were implanted compared totransistors where only the fourth impurities was implanted. Further,implanting the third impurities reduces diffusion of the fourthimpurities, and a concentration of the fourth impurities in the dopedregions 36 can be increased. As a result, contact resistance can belowered. For example, in experimental data, source resistance (R_(s))can be reduced by at least 20% through the implantation of a relativelylow formation enthalpy impurities (e.g., the third impurities in thedoped regions 34) prior to the implantation of the relatively highformation enthalpy impurities (e.g., the fourth impurities in the dopedregions 36). For example, the additional As implantation can improve Rsby 20% or more compared to a structure without this As implantation.

The doped regions 36 may include regions 36A, 36B, and 36C, and a dopantconcentration of fourth impurities in the regions 36A, 36B, and 36C maybe different. For example, a concentration of the fourth impurities maybe higher in the regions 36B than in the regions 36A, and aconcentration of the fourth impurities may be higher in the regions 36Cthan in the regions 36B. The concentration of the fourth impurities ineach of the regions 36A, 36B, and 36C may be varied or constant. Forexample, the doped region 36 may have a gradient concentration of thefourth impurities that increases in a direction towards a top surface ofthe epitaxial source/drain regions 82 (as indicated by arrow 38).Likewise, the concentration of the third impurities in the region 34 maybe constant or varied. For example, the doped region 34 may have agradient concentration of the third impurities that increases in thedirection of arrow 38.

FIG. 15D illustrates a graph 250 of impurity concentration in theepitaxial source/drain region 82 in an embodiment device such as along acenter line of an epitaxial source/drain region 82. Line 252 representsa concentration of the fourth impurities (e.g., phosphorus dimer) whileline 254 represents a concentration of the third impurities (e.g.,arsenic). As illustrated, a post anneal concentration of the fourthimpurities (e.g., phosphorus dimer) may be greater than 10²² cm⁻³ in acontact area (e.g., the doped regions 36C) of the epitaxial source/drainregions 82. It has been observed that by providing a doped region withthis concentration, source/drain contact resistance is advantageouslyreduced. Other impurity concentration profiles are also possible inother embodiments.

As explained above, a profile of the doped regions 34 and 36 may beadjusted by varying process parameters (e.g., rotation angle) of theimplantation processes 26 and 30. FIG. 15A illustrates a profile that isachieved by not rotating the wafer 10 around the process chamber duringthe first implantation process 26 and the second implantation process30. FIG. 16 illustrates an alternate embodiment where the wafer 10 isrotated 90° twice during each of the first implantation process 26 andthe second implantation process 30. In FIG. 16, like reference numeralsindicate like elements formed using like processes as FIG. 15A. Asillustrated by FIG. 16, the doped regions 34 may be disposed on sides ofthe doped regions 36, and the doped regions 34 may further extend underthe gate spacers 86/dummy gates 72. The doped regions 36 may extendfurther into the epitaxial source/drain regions 82 than the dopedregions 34. FIG. 17 illustrates an alternate embodiment where the firstimplantation 26 includes rotating the wafer 10 by 90° four times, andthe second implantation 30 does not include rotating the wafer 10. InFIG. 17, like reference numerals indicate like elements formed usinglike processes as FIG. 15A. As illustrated by FIG. 17, the doped regions34 may be disposed on sides of the doped regions 36, and the dopedregions 34 may further extend under the gate spacers 86/dummy gates 72.The doped regions 34 may likewise extend under the gate spacers 86/dummygates 72, and the doped regions 36 may extend further into the epitaxialsource/drain regions 82 than the doped regions 34. In each of theembodiments of FIGS. 16 and 17, the doped regions 34 includes regions34A and 34B, and an impurities concentration of the third impurities inthe region 34A may be greater than the region 34B. The impuritiesconcentration in each of the regions 34A and/or 34B may be constant orvaried. Other configurations of the doped regions 34 and 36 are alsopossible.

The epitaxial source/drain regions 82 in the p-type region 50P may beformed by masking the n-type region 50N and etching source/drain regionsof the fins 52 in the p-type region 50P to form recesses in the fins 52.Then, the epitaxial source/drain regions 82 in the p-type region 50P areepitaxially grown in the recesses. The epitaxial source/drain regions 82may include any acceptable material, such as appropriate for p-typeFinFETs. For example, if the fin 52 is silicon, the epitaxialsource/drain regions 82 in the p-type region 50P may comprise materialsexerting a compressive strain in the channel region 58, such assilicon-germanium, boron doped silicon-germanium, germanium, germaniumtin, or the like. The epitaxial source/drain regions 82 in the p-typeregion 50P may have surfaces raised from respective surfaces of the fins52 and may have facets.

In FIGS. 18A and 18B, a first interlayer dielectric (ILD) 88 isdeposited over the structure illustrated in FIGS. 10A and 10B. The firstILD 88 may be formed of a dielectric material, and may be deposited byany suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD.Dielectric materials may include phospho-silicate glass (PSG),boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG),undoped silicate glass (USG), or the like. Other insulation materialsformed by any acceptable process may be used. In some embodiments, acontact etch stop layer (CESL) 87 is disposed between the first ILD 88and the epitaxial source/drain regions 82, the masks 74, and the gatespacers 86. The CESL 87 may comprise a dielectric material, such as,silicon nitride, silicon oxide, silicon oxynitride, or the like, havinga lower etch rate than the material of the overlying first ILD 88.

In FIGS. 19A and 19B, a planarization process, such as a CMP, may beperformed to level the top surface of the first ILD 88 with the topsurfaces of the dummy gates 72 or the masks 74. The planarizationprocess may also remove the masks 74 on the dummy gates 72, and portionsof the gate seal spacers 80 and the gate spacers 86 along sidewalls ofthe masks 74. After the planarization process, top surfaces of the dummygates 72, the gate seal spacers 80, the gate spacers 86, and the firstILD 88 are level. Accordingly, the top surfaces of the dummy gates 72are exposed through the first ILD 88. In some embodiments, the masks 74may remain, in which case the planarization process levels the topsurface of the first ILD 88 with the top surfaces of the top surface ofthe masks 74.

In FIGS. 20A and 20B, the dummy gates 72, and the masks 74 if present,are removed in an etching step(s), so that recesses 90 are formed.Portions of the dummy dielectric layer 60 in the recesses 90 may also beremoved. In some embodiments, only the dummy gates 72 are removed andthe dummy dielectric layer 60 remains and is exposed by the recesses 90.In some embodiments, the dummy dielectric layer 60 is removed fromrecesses 90 in a first region of a die (e.g., a core logic region) andremains in recesses 90 in a second region of the die (e.g., aninput/output region). In some embodiments, the dummy gates 72 areremoved by an anisotropic dry etch process. For example, the etchingprocess may include a dry etch process using reaction gas(es) thatselectively etch the dummy gates 72 with little or no etching of thefirst ILD 88 or the gate spacers 86. Each recess 90 exposes and/oroverlies a channel region 58 of a respective fin 52. Each channel region58 is disposed between neighboring pairs of the epitaxial source/drainregions 82. During the removal, the dummy dielectric layer 60 may beused as an etch stop layer when the dummy gates 72 are etched. The dummydielectric layer 60 may then be optionally removed after the removal ofthe dummy gates 72.

In FIGS. 21A and 21B, gate dielectric layers 92 and gate electrodes 94are formed for replacement gates. FIG. 21C illustrates a detailed viewof region 89 of FIG. 21B. Gate dielectric layers 92 one or more layersdeposited in the recesses 90, such as on the top surfaces and thesidewalls of the fins 52 and on sidewalls of the gate seal spacers80/gate spacers 86. The gate dielectric layers 92 may also be formed onthe top surface of the first ILD 88. In some embodiments, the gatedielectric layers 92 comprise one or more dielectric layers, such as oneor more layers of silicon oxide, silicon nitride, metal oxide, metalsilicate, or the like. For example, in some embodiments, the gatedielectric layers 92 include an interfacial layer of silicon oxideformed by thermal or chemical oxidation and an overlying high-kdielectric material, such as a metal oxide or a silicate of hafnium,aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, andcombinations thereof. The gate dielectric layers 92 may include adielectric layer having a k value greater than about 7.0. The formationmethods of the gate dielectric layers 92 may include Molecular-BeamDeposition (MBD), ALD, PECVD, and the like. In embodiments whereportions of the dummy gate dielectric 60 remains in the recesses 90, thegate dielectric layers 92 include a material of the dummy gatedielectric 60 (e.g., SiO₂).

The gate electrodes 94 are deposited over the gate dielectric layers 92,respectively, and fill the remaining portions of the recesses 90. Thegate electrodes 94 may include a metal-containing material such astitanium nitride, titanium oxide, tantalum nitride, tantalum carbide,cobalt, ruthenium, aluminum, tungsten, combinations thereof, ormulti-layers thereof. For example, although a single layer gateelectrode 94 is illustrated in FIG. 21B, the gate electrode 94 maycomprise any number of liner layers 94A, any number of work functiontuning layers 94B, and a fill material 94C as illustrated by FIG. 21C.After the filling of the recesses 90, a planarization process, such as aCMP, may be performed to remove the excess portions of the gatedielectric layers 92 and the material of the gate electrodes 94, whichexcess portions are over the top surface of the ILD 88. The remainingportions of material of the gate electrodes 94 and the gate dielectriclayers 92 thus form replacement gates of the resulting FinFETs. The gateelectrodes 94 and the gate dielectric layers 92 may be collectivelyreferred to as a “gate stack.” The gate and the gate stacks may extendalong sidewalls of a channel region 58 of the fins 52.

The formation of the gate dielectric layers 92 in the n-type region 50Nand the p-type region 50P may occur simultaneously such that the gatedielectric layers 92 in each region are formed from the same materials,and the formation of the gate electrodes 94 may occur simultaneouslysuch that the gate electrodes 94 in each region are formed from the samematerials. In some embodiments, the gate dielectric layers 92 in eachregion may be formed by distinct processes, such that the gatedielectric layers 92 may be different materials, and/or the gateelectrodes 94 in each region may be formed by distinct processes, suchthat the gate electrodes 94 may be different materials. Various maskingsteps may be used to mask and expose appropriate regions when usingdistinct processes.

In FIGS. 22A and 22B, a gate mask 96 is formed over the gate stack(including a gate dielectric layer 92 and a corresponding gate electrode94), and the gate mask may be disposed between opposing portions of thegate spacers 86. In some embodiments, forming the gate mask 96 includesrecessing the gate stack so that a recess is formed directly over thegate stack and between opposing portions of gate spacers 86. A gate mask96 comprising one or more layers of dielectric material, such as siliconnitride, silicon oxynitride, or the like, is filled in the recess,followed by a planarization process to remove excess portions of thedielectric material extending over the first ILD 88.

As also illustrated in FIGS. 22A and 22B, a second ILD 108 is depositedover the first ILD 88. In some embodiments, the second ILD 108 is aflowable film formed by a flowable CVD method. In some embodiments, thesecond ILD 108 is formed of a dielectric material such as PSG, BSG,BPSG, USG, or the like, and may be deposited by any suitable method,such as CVD and PECVD. The subsequently formed gate contacts 110 (FIGS.16A and 16B) penetrate through the second ILD 108 and the gate mask 96to contact the top surface of the recessed gate electrode 94.

In FIGS. 23A and 23B, gate contacts 110 and source/drain contacts 112are formed through the second ILD 108 and the first ILD 88 in accordancewith some embodiments. Openings for the source/drain contacts 112 areformed through the first and second ILDs 88 and 108, and openings forthe gate contact 110 are formed through the second ILD 108 and the gatemask 96. The openings may be formed using acceptable photolithographyand etching techniques. A liner (not shown), such as a diffusion barrierlayer, an adhesion layer, or the like, and a conductive material areformed in the openings. The liner may include titanium, titaniumnitride, tantalum, tantalum nitride, or the like. The conductivematerial may be copper, a copper alloy, silver, gold, tungsten, cobalt,aluminum, nickel, or the like. A planarization process, such as a CMP,may be performed to remove excess material from a surface of the ILD108. The remaining liner and conductive material form the source/draincontacts 112 and gate contacts 110 in the openings. An anneal processmay be performed to form a silicide at the interface between theepitaxial source/drain regions 82 and the source/drain contacts 112. Thesource/drain contacts 112 are physically and electrically coupled to theepitaxial source/drain regions 82, and the gate contacts 110 arephysically and electrically coupled to the gate electrodes 106. As aresult of the first implantation process 26 and the second implantationprocess 30, a concentration of the fourth impurities (e.g., phosphorusdimer, or the like) may be increased in an area where the source/draincontacts 112 connect to the epitaxial source/drain regions 82. As aresult, a contact resistance of the source/drain contacts 112 can beadvantageously reduced. The source/drain contacts 112 and gate contacts110 may be formed in different processes, or may be formed in the sameprocess. Although shown as being formed in the same cross-sections, itshould be appreciated that each of the source/drain contacts 112 andgate contacts 110 may be formed in different cross-sections, which mayavoid shorting of the contacts.

The disclosed FinFET embodiments could also be applied to nanostructuredevices such as nanostructure (e.g., nanosheet, nanowire,gate-all-around, or the like) field effect transistors (NSFETs). In anNSFET embodiment, the fins are replaced by nanostructures formed bypatterning a stack of alternating layers of channel layers andsacrificial layers. Dummy gate stacks and source/drain regions areformed in a manner similar to the above-described embodiments. After thedummy gate stacks are removed, the sacrificial layers can be partiallyor fully removed in channel regions. The replacement gate structures areformed in a manner similar to the above-described embodiments, thereplacement gate structures may partially or completely fill openingsleft by removing the sacrificial layers, and the replacement gatestructures may partially or completely surround the channel layers inthe channel regions of the NSFET devices. ILDs and contacts to thereplacement gate structures and the source/drain regions may be formedin a manner similar to the above-described embodiments. A nanostructuredevice can be formed as disclosed in U.S. Patent Application PublicationNo. 2016/0365414, which is incorporated herein by reference in itsentirety.

Various embodiments include implanting two different types of dopantsinto a source/drain region for improved junction abruptness (e.g.,reduced leakage current) and reduced source/drain contact resistance. Inan embodiment method, first dopants are implanted into a source/drainregion followed by an implantation of second dopants. The first dopantsmay have a lower formation enthalpy than the second dopants. Forexample, the first dopants may comprise arsenic, carbon, antimony, orthe like, and the second dopants may comprise phosphorus, or the like.In particular embodiments, the arsenic is implanted into thesource/drain regions followed by a phosphorus dimer (P2) implantation.As a result of its lower formation enthalpy, the first dopants are moreattracted to and form more stable bonds with vacancies in thesource/drain region. For example, the first dopants may be used toreduce diffusion of the second dopants and reduce the binding of thesecond dopants with the vacancies. By reducing diffusion of the seconddopant, a higher concentration of the second dopant may be achieved in acontact area of the source/drain region, thereby reducing source/draincontact resistance. Further, the use of two different elements asdopants allows for a junction with improved abruptness and lessdiffusion, thereby providing improved short channel control (e.g., tocounter the effects of drain-induced barrier lowering (DIBL) in advancedprocess nodes), reduced leakage, and improved device performance.Various embodiments may provide one or more of the followingnon-limiting advantages: improved junction abruptness, reduced diffusionof the second dopants, and reduced source/drain contact resistance.

In accordance with some embodiments, a method includes forming asource/drain region in a semiconductor fin; after forming thesource/drain region, implanting first impurities into the source/drainregion; after implanting the first impurities, implanting secondimpurities into the source/drain region, wherein the first impuritieshave a lower formation enthalpy than the second impurities; and afterimplanting the second impurities, annealing the source/drain region. Insome embodiments, the first impurities comprise arsenic, antimony, orcarbon. In some embodiments, the second impurities comprise phosphorus.In some embodiments, implanting the second impurities into thesource/drain region comprises implanting phosphorus dimer into thesource/drain region. In some embodiments, forming the source/drainregion comprises: etching a recess in the semiconductor fin; epitaxiallygrowing a first epitaxy region in the recess; in-situ doping the firstepitaxy region with third impurities while epitaxially growing the firstepitaxy region; epitaxially growing a second epitaxy region in therecess and over the first epitaxy region; and in-situ doping the secondepitaxy region with fourth impurities while epitaxially growing thesecond epitaxy region, wherein the third impurities are a differentelement than the fourth impurities. In some embodiments, the thirdimpurities are a same element as the first impurities. In someembodiments, annealing the source/drain region comprises: performing amicrosecond anneal (μSSA) on the source/drain region; and afterperforming the μSSA, performing a laser spike anneal (LSA) on thesource/drain region.

In accordance with some embodiments, a method includes etching a recessin a semiconductor fin; epitaxially growing a source/drain region in therecess; after epitaxially growing the source/drain region, implantingthe source/drain region with arsenic; after implanting the source/drainregion with arsenic, implanting the source/drain region with phosphorusdimer; and after implanting the source/drain region with phosphorusdimer, activating the arsenic and the phosphorus dimer with an annealingprocess. In some embodiments, implanting the source/drain region withphosphorus dimer comprises using an implantation dose in a range of 10¹⁸cm⁻³ to 10²² cm⁻³. In some embodiments, no annealing process isperformed between implanting the source/drain region with arsenic andimplanting the source/drain region with phosphorus dimer. In someembodiments, implanting the source/drain region with arsenic comprisesrotating a wafer comprising the semiconductor fin by 90° twice. In someembodiments, implanting the source/drain region with arsenic comprisesrotating a wafer comprising the semiconductor fin by 45° four times. Insome embodiments, implanting the source/drain region with arseniccomprises not rotating a wafer comprising the semiconductor throughoutan entire duration of implanting the source/drain region with arsenic.

In accordance with some embodiments, a device includes a semiconductorsubstrate; a gate stack at a top surface of the semiconductor substrate;a source/drain region adjacent the gate stack, wherein the source/drainregion comprises a first epitaxy region comprising first impurities; afirst doped region comprising second impurities in the first epitaxyregion; and a second doped region comprising third impurities in thefirst epitaxy region, the second impurities having a lower formationenthalpy than the third impurities, the first doped region surroundingsides of the second doped region. In some embodiments, the source/drainregion further comprises a second epitaxy region surrounding the firstepitaxy region, wherein the second epitaxy region comprises fourthimpurities, and the fourth impurities are a different element than thefirst impurities. In some embodiments, the second doped region extendslower than the first doped region. In some embodiments, the first dopedregion covers a bottom of the second doped region. In some embodiments,the second impurities are arsenic, and the third impurities comprisephosphorus. In some embodiments, a concentration of the third impuritiesincreases in a direction towards a top surface of the source/drainregion. In some embodiments, the device further comprises a source/draincontact extending into the second doped region, wherein a concentrationof the third impurities at the source/drain contact is at least 10²³cm⁻³.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A device comprising: a semiconductor substrate; agate stack at a top surface of the semiconductor substrate; asource/drain region adjacent the gate stack, wherein the source/drainregion comprises a first epitaxy region comprising first impurities; afirst doped region comprising second impurities in the first epitaxyregion; and a second doped region comprising third impurities in thefirst epitaxy region, the second impurities having a lower formationenthalpy than the third impurities, the first doped region surroundingsides of the second doped region such that the second impurities extendfrom a top of the semiconductor substrate to along sides of the seconddoped region.
 2. The device of claim 1, wherein the source/drain regionfurther comprises a second epitaxy region surrounding the first epitaxyregion, wherein the second epitaxy region comprises fourth impurities,and the fourth impurities are a different element than the firstimpurities.
 3. The device of claim 1, wherein the second doped regionextends lower than the first doped region.
 4. The device of claim 1,wherein the second impurities of the first doped region extend from thetop of the semiconductor substrate to below the second doped region. 5.The device of claim 1, wherein the second impurities are arsenic, andthe third impurities comprise phosphorus.
 6. The device of claim 1,wherein a concentration of the third impurities in the second dopedregion increases in a direction towards a top surface of thesource/drain region.
 7. The device of claim 1 further comprising asource/drain contact extending into the second doped region, wherein aconcentration of the third impurities at the source/drain contact is atleast 10²³ cm⁻³.
 8. A device comprising: a gate stack at a top surface asemiconductor substrate; a source/drain region adjacent the gate stack,wherein the source/drain region comprises: a first epitaxy regioncomprising first impurities; a second epitaxy region extending alongsidewalls and below the first epitaxy region, the second epitaxy regioncomprising second impurities different from the first impurities; anarsenic-doped region extending into the first epitaxy region; and aphosphorus-doped region extending into the first epitaxy region, whereinarsenic of the arsenic-doped region extends along sides and below thephosphorus-doped region.
 9. The device of claim 8, wherein thephosphorus-doped region comprises phosphorus dimer.
 10. The device ofclaim 8, wherein the arsenic-doped region further extends into thesecond epitaxy region.
 11. The device of claim 8, wherein thephosphorus-doped region further extends into the second epitaxy region.12. The device of claim 8, wherein the first impurities are phosphorus.13. The device of claim 12, wherein the second impurities are arsenic.14. The device of claim 8 further comprising a gate spacer alongsidewalls of the gate stack, wherein the gate spacer overlaps both thearsenic-doped region and the phosphorus-doped region.
 15. A devicecomprising: a gate stack at a top surface a semiconductor substrate; asource/drain region adjacent the gate stack, wherein the source/drainregion comprises a first epitaxy region comprising first n-type dopants;an arsenic-doped region extending into the first epitaxy region; and aphosphorus-doped region extending into the first epitaxy region, whereinarsenic of the arsenic-doped region extends along sides of thephosphorus-doped region, and wherein the arsenic of the arsenic-dopedregion further extends directly under the gate stack.
 16. The device ofclaim 15, wherein the source/drain region further comprises a secondepitaxy region extending along sidewalls and below the first epitaxyregion, the second epitaxy region comprising second n-type dopantsdifferent from the first n-type dopants.
 17. The device of claim 15,wherein phosphorus of the phosphorus-doped region extends directly undera gate spacer, the gate spacer being disposed on a sidewall of the gatestack.
 18. The device of claim 17, the phosphorus of thephosphorus-doped region further extends directly under the gate stack.19. The device of claim 15, wherein phosphorus of the phosphorus-dopedregion extends lower than the arsenic of the arsenic-doped region. 20.The device of claim 15, wherein an phosphorus concentration of thephosphorus-doped region increases in a direction towards a top surfaceof the source/drain region.